Electronic totalizer element



Nov. 26, 1957 A. cHAlMowlcz ELECTRONIC TOTALIZER ELEMENT 3 Sheets-Sheet 1 Filed July 3. 1951 u ,b ,l w mmf@ .0 www Nov. 26, 1957 A. cHAlMowlcz ELECTRONIC TOTALIZER ELEMENT 3 Sheets-snee?l 2 Filed July 3. 1951 Nov. 26, 1957 A. cHAlMowlcz 2,814,441

ELECTRONIC TOTALIZER ELEMENT Filed July :5, -1951 I s sheets-sheet 5 ELECTRNIC TOTALIZER ELEMENT Adam Chairnowicz, Paris, France, assignor to Compagnie des Machines Bull (Societe Anonyme), Paris, France Application July 3, 1951, Serial No. 234,958

Claims priority, application France July 7, 1950 Claims. (Cl. 23S- 92) The present invention relates to electronic totalizers in which the base element consists of a decade of a biquinary impulse counter.

It wil1 be recalled that in a biquinary notati-on system each digit of a decimal unit order is expressed by two terms, one of which represents one of the two possibilities of a first group of two alternatives and the other one of the tve possibilities of a second group of live alternatives. Consequently, a biquinary electronic decade will normally comprise an electronic trigger circuit having two conditions of equilibrium, which is representative of the said first group, an electronic combination having ve conditions of stable equilibrium, which is representative of the second group, and members for connecting the groups together and to the other decades or impulse counters.

Biquinary electronic counters are already known, yand are referred to, for example, in French Patent No. 939,453 of the 24th December, 1946 and in United States Patent No. 2,436,963 of the 26th February, 1944. ln the lirst of these two patents, the group of vlive comprises only ive valves and is `of the general multi-vibrator type; certain constructional difficulties are encountered therewith when it is desired to obtain high reliability of operation on this principle and with this number of valves. The second patent proposes for the group of 5, ten valves connected in tive pairs of flip flops, which represents a large number of valves per decade.

The present invention relates to electronic totalizers or accumulators in which each decade or order comprises a rst group consisting of a single trigger or flip flop circuit (of the Eccles-Jordan or a similar type), a second group consisting of three trigger circuits of the same type and a connecting member controlled by a fifth impulse emanating from the second group, returning it to zero and actuating the trigger circuit of the rst group.

The present invention concerns electronic totalizers operating by the series injection of impulses and comprising for each unit order a biquinary-decade as used in impulse counters of the preceding type and associated members. l

rates Patent 0 It is to be noted that in the foregoing there is meant l by series injection `of impulses the fact that these impulses are set up one after the other and equally distributed in point of time at a common input, and that the essential difference in the meaning of the terms counter and totalizer resides in that the counter sim- ICC selectively control the admission or blocking of the impulses applied to the totalizer by an impulse generator. A decimal figure for instance 9 thus introduced into a decade or element of a totalizer according to the invention is represented by five impulses emitted at different times in accordance with the following code: The four rst impulses are all of weight equal to one, while the lifth impulse is of weight ve. Consequently the invention further relates to a totalizer element or accumulator element in which the impulses of weight one pass through one channel and those of weight tive through another channel.

In accordance with an important feature of the invention, in a totalizer element of this form, each decimal figure intended to be introduced in this coded form into the said totalizer element occupies only live places or elementary times. Thus, the storage of the numbers constituted by such digits with a View to their subsequent introduction into a totalizer element according to the invention requires only a relatively small memory arrangement, the said arrangement being in any case smaller than that required by ordinary counters and the elements thereof normally being ten in number for each decimal ligure.

The features and advantages of the invention will appear more clearly from the following description, with reference to the accompanying drawings, in which:

Figure 1 shows diagrammatically a biquinary impulse counter,

Figures 2 and 3 are diagrams showing different states of the triggers shown in Figure l,

Figure 4 is a modication of Figure 1,

Figure 5 is a diagram similar to Figures 2 and 3,

Figure 6 shows diagrammatically an accumulator element according to the invention,

Figure 7 is a modilication of Figure 6, and

Figure 8 is another diagram of an accumulator element.

Fig. 9 is a diagram lof a Hip-flop with an asymetrical input,

Fig. l0 is a diagram of a one-shot multivibrator,

Fig. 11 is a diagram for a gate.

The trigger arrangement shown in Fig. 9 is a conventional ip-flop, the working of which has been known since Eccles and Jordan. It is known that such a system possesses two states of equilibrium which are exclusive of one another; the system passes from one said state to the other, whenever a negative impulse is simultaneously applied by means of common input X to both control grids 20 and 21 of the two triodes here united in the same bulb. To this end, the negative impulses are applied at the X input and thus transmitted through unidirectional elements 25 and 26, and through capacitors 23 and 24 to said control grids. This may be called the symmetrical input to the flip-flop. A so called asymmetrical input is also provided at D1 through the intermediary -of unidirectional element 27 connected as shown. vIt is seen from the iigure that a negative potential applied to D1 can pass through 23 to control grid 2t), but due to the presence lof 25, the same potential is not applied to control grid 21. It follows that the application of an impulse to a said 'asymmetrical input only triggers the Hip-flop if prior to said application, it is in a determined one of its two states of equilibrium.

In Figure l there isdiagrammatically illustrated a biquinary impulse counter comprising four ecctronic triggers or flip flops A, B, C and D. ln this figure, the triggers are shown in the position O, the upper valve of each trigger being conducting and the signalling lamp, for example 30, being extinguished. The successive impulses are applied to E. This input E corresponds to the symmetrical input X of' the trigger circuit o f Fig. 9.

With the connections shown in Figure 1, a first negative impulse changes over A, which passes to the condition 1, B and C remaining unchanged. A second impulse returns A to the condition and the resulting negative impulse is transmitted from the output of A to B, which is changed over to l. The third impulse changes over A without afecting B, and the fourth impulse changes over A, B and C. The condition of A, B, C after the fourth impulse is diagrammatically illustrated in Figure 2, the condition of D not having changed.

At G is provided a member (called a gate in English technical literature) which is such that, on application of a sutliciently negative voltage at 9 and a negative impulse at the line 8 (connected to E), a negative impulse is set up on line 1l). Such members are known and may consist, for example, of a diode arrangement, a multi-grid valve, or an association of valves, etc. lt is preferable and realizable to use a singletype of gate, controlled for example by negative impulses, and delivering negative impulses. A gate of this type is shown in Fig. 11 (having a twocontrolgrid-bulb 28, biased to the cut-off, and having its output on the cathode circuit). Through wire 9, a control electrode of gate G is subjected to voltages under control of terminal L01 or lower output of the trigger circuit of Fig. 9. The output impulse resulting on the liuc` 'ril from the fifth impulse is employed for two purposes: On the one hand it acts on the trigger D representing the group of two already mentioned, and on the other hand it is applied through the retardation element e and the line 11 to the asymmetrical inputs of A, B and C. The delay time of element 0 should substantially be equal to the duration of one input impulse. The said asymmetrical inputs correspond each to input Dl of the trigger circuit in Fig, 9, which also shows one unidirectional cell 27, inserted in the reset input wire. This impulse resulting from the fth impulse is applied t0 A, B and C through the connection 11, and returns A and C to zero, and is transmitted to D, which is changed over. The nal conditions of the triggers are diagrammatically illustrated in Figure 3. The cycle of the following ve impulses is identical, except that D changes over at the tenth impulse in the opposite direction, whereby all the triggers are returned to the conditions shown in Figure 1, a negative carry-over impulse being emitted at S. lt will be seen that with this circuit arrangement the trigger A is returned to the condition "0 after having been moved by an impulse from the condition "0 to the condition 1. A represents the digit l, B the digit 2, C the digit 4 and D the digit 5, the dgit 3 being represented by the triggers A and B in the l condition.

Figure 4 is a modification of Figure l, in which there is no gate G, but a simple feedback connection through the conductor 12 between the trigger C and the triggers A and B. Up to the fourth impulse, the operation is the same as in the preceding case, i. e. the fourth impulse commences by positioning the system in the condition shown in Figure 2. However, since C changes over at the fourth impulse, an impulse of negative voltage is set up in the plate circuit of the lower valve and from C it is passed through 12 to the grids of the upper valves of A and B, which are brought below the cut-olf. The condition of the system is shown in Figure 5. The arrival of the fth impulse returns the lirst three triggers to zero and changes over D, due to the operation of the carryovers.

In contra distinction to the preceding arrangement, if A again represents the digit 1, B the digit 2 and D the digit 5, C only representsl 1 in the position of nal equilibrium. That is to say, the digit 4 is represented by A, B and C in the condition 1 and D in the condition "0 as shown in Figure 5. The digit 9 is identically represented except that D is in the condition 1.

Figure 6 shows the `diagram of a totalizer element in which the biquinary impulse counter of Figure 1 is employed. To E1 are applied the negative impulses to be totalled, marked 1, 2, 3, 4, 5, while the pilot impulse p is applied to E2. The pilot impulse passes through a delay line R comprising separate elements each having a suitable delay t equal to the interval of time between two consecutive impulse emissions. These delay elements may be in the form of an electromagnetic delay network, for example following the technique developed by S. Moskowicz and Raeder in the reviev.l Radio- News, No. 38, of April 1948, pp. l5, 18, 30 and 31. The outputs of the said elements, with the exception of the last, are connected by unidirectional cells 14 and the connection 13 to the input of the control means for the gate G'. For each impulse transmitted to 13, G opens and allows the impulse applied to El to pass, the sai-:l impulse passing at this instant. Another gate G" opens in line 17 due to the impulse set up at the end of R at the time 5, and a single impulse can pass, this impulse being applied by 10 to D, which is changed over. A unidircctional element 15 prevents this impulse from passing to the connection 11 (or the action of the connection 1i! on D takes place at a different point permitting sufhcient dccoupling to prevent the transmission of this impulse to 11).

It will first be assumed that the decade or totalizer element considered in the totalizer is in the zero position. The introduction of a number of impulses weighted l lower than or equal to 4 is registered as in a counter in the assembly ABC, or the introduction of an impulse Weighted ve is separately registered in D. It will now be assumed that a 3 has already been registered in the counter ABC. If a train of three impulses weighted l occurs during a subsequent totalling cycle, the first impulse is added in ABC and trigger C unblocks G, the second impulse causes the resetting of ABC and is registered in D through G and 15, and the third impulse changes over A. It will be seen that the addition 3-|-3=6 has been eected.

Figure 8 is a diagram of a totalizer element similar to that of Fig. 6, and giving similar results, but embodying the biquinary counter of Fig. 4.

It is clear that, instead of producing four impulses from the pilot impulse through a delay line comprising separate elements, it is possible to employ four separate impulses supplied by a distributor common to all the decades or elements of the totalizer. In this case, the line 13 is only a single input, and the input of G is simply controlled by a delay line comprising a single network having the total delay time necessary for the passage of the impulse 5.

It is also possible without departing from the scope of the invention to replace the delay line R by another device, such as an asymmetrical multi'vibrator or a trigger of the one shot type (having only a single condition of stable equilibrium). The one-shot multivibrator, also called a mono-stable trigger circuit, may be realized, for example, according to that shown in Fig. l0, which is controlled by negative impulses applied on the terminal marked input As the control grid of the right-hand pentode is returned to terminal +B through resistor 18, this trigger circuit has only one stable state of conduction, in which the right-hand pentode is conducting and the left-hand pentode non-conducting. When this circuit is triggered to its unstable condition, the right-hand pentode remains non-conducting and the lefthand pentode remains conducting for a time chieiiy dependent on the values of capacitor 19 and resistor 18. Figure 7 shows by way of non-limitative example the diagram of such an arrangement in which F is a monostable trigger of the one shot type comprising two outputs (that is U02 and L02, `in Fig. l0) which are con nected respectively to the control inputs of G', and G". The pilot impulse p changes over F so as to bring about the unblocking of G' and the blocking of G for a time of between 4 and 5 elementary times t, for example 4.5 elementary times (the elementary time t being the interval of time between two impulses of the generator,

applied to E1). At the end of this period of time F again changes over by reason of its internal construction and opens G, thus permitting1 the passage of the impulse at the time 5 by G", which impulse is registered in D.

It is to be noted that the gate G could be of a dilerent type from the gates G and G". For instance, gate G could be opened by positive voltages, while the other two should be opened by negative voltages. If a gate G of this type is used, in the form of a pentode tube, for example, its control electrode or screen grid should be connected to output U01, instead of being connected to output L01 of the trigger of Fig. 9, assumed to be representing trigger C of Figs. 6 or 7. It is possible to envisage modications of the invention in which these gates are of different nature from those referred to in the foregoing, taking the required voltages at suitable points, and other modified embodiments, without modifying the fundamental components of the decade, and without departing from the scope of the invention.

The totalizer element according to the invention comprises, as will be seen, relatively few valves, while affording the advantage already mentioned of an associated memory (not shown in the figures) of relatively small size.

I claim:

1. Accumulator element for accumulating numbers, the significant digits of which are each represented in the coded decimal system of notation by a number of input impulses, that is one to four l Weighted impulses for the digits 1 to 4, and one 5 Weighted impulse for the digit 5 and the digits greater than 5, this element comprising an inlet terminal for receiving said input impulses which have different time relationships with respect to a pilot impulse defining a totalling cycle, a quinary counter including three bi-stable trigger circuits respectively assigned to the values 1, 2 and 4, a binary counter with one bi-stable trigger circuit assigned to the value 5, and circuit switching means controlled by said pilot impulse for passing the l weighted impulses, if any, from said inlet terminal to the inlet of said quinary counter and for passing the "5 Weighted impulse, if any, from said inlet terminal to the inlet of said binary counter.

2. Accumulator element as claimed in claim 1, in which said circuit switching means comprise a first gate arrangement and a second gate arrangement, connected between said inlet terminal and the inlets of said quinary counter and said binary counter respectively, and a series of time delay networks which receive said pilot impulse and derive therefrom control impulses applied to both gate arrangements to make them operative at times coincident w32 the reception of the dierently weighted input imp es.

3. Accumulator element as claimed in claim 2, in which a third gate arrangement, connected between the output of said first gate arrangement and the inlet of said binary counter, is controlled by the trigger circuit assigned to the value 4 in said quinary counter, so that, when the latter receives an l weighted impulse which changes its contents from 4 to 5, said third gate arrangement passes a live carry impulse to said binary counter.

4. Accumulator element as claimed in claim 1, in which said circuit switching means comprise a first gate arrangement and a second gate arrangement which connect said inlet terminal to the inlets of said quinary counter and of said binary counter respectively, and a mono-stable trigger circuit which controls the respective operative conditions of said both gate arrangements and receives said pilot impulse, thereby assuming a transient state during which it causes said first gate arrangement to pass the 1 weighted impulses, if any, from the inlet terminal to said quinary counter.

5. Accumulator element as claimed in claim 4, in which a third gate arrangement connects the inlet of said quinary counter to the inlet of said binary counter, this gate arrangement being controlled by the trigger circuit assigned to the value 4 in said quinary counter, so that, when the latter receives any l weighted impulse which changes its contents from 4 to 5, said third gate arrangement passes said impulse as a five carry impulse to said binary counter.

References Cited in the tile of this patent UNITED STATES PATENTS 2,310,105 Michel Feb. 2, 1943 2,470,716 Overbeek May 17, 1949 2,484,115 Palmer et al Oct. 11, 1949 2,486,809 Stibitz Nov. l, 1949 2,528,394 Sharpless Oct. 3l, 1950 2,563,102 Crosman et al Aug. 7, 1951 2,566,918 Bergfors Sept. 4, 1951 2,566,933 Dickinson Sept. 4, 1951 2,577,075 Dickinson Dec. 4, 1951 2,626,752 Williams Jan. 27, 1953 2,630,969 Schmidt Mar. l0, 1953 2,634,052 Bloch Apr. 7, 1953 2,635,229 Gloess et al. Apr. 14, 1953 OTHER REFERENCES Third Interim Progress Report by the Institute of Advanced Study; Princeton, New Jersey, January 1, 1948, pages 119-137. 

